Mdthbs

lscpu

If you care only about the sizes, try lscpu from util-linux.

Example

$ lscpu

Architecture:          x86_64

CPU op-mode(s):        32-bit, 64-bit

Byte Order:            Little Endian

CPU(s):                4

On-line CPU(s) list:   0-3

Thread(s) per core:    2

Core(s) per socket:    2

Socket(s):             1

NUMA node(s):          1

Vendor ID:             GenuineIntel

CPU family:            6

Model:                 37

Model name:            Intel(R) Core(TM) i5 CPU       M 560  @ 2.67GHz

Stepping:              5

CPU MHz:               1199.000

BogoMIPS:              5319.88

Virtualization:        VT-x

L1d cache:             32K

L1i cache:             32K

L2 cache:              256K

L3 cache:              3072K

NUMA node0 CPU(s):     0-3

x86info

There should be also package/command called x86info. Assuming you have i386/x86_64, x86info -c should provide more detailed information about caches.

Example

$ x86info -c

x86info v1.30.  Dave Jones 2001-2011

Feedback to <davej@redhat.com>.



Found 4 identical CPUs

Extended Family: 0 Extended Model: 2 Family: 6 Model: 37 Stepping: 5

Type: 0 (Original OEM)

CPU Model (x86info's best guess): Core i7 (Nehalem) [Clarkdale/Arrandale]

Processor name string (BIOS programmed): Intel(R) Core(TM) i5 CPU       M 560  @ 2.67GHz



Cache info

 L1 Instruction cache: 32KB, 4-way associative. 64 byte line size.

 L1 Data cache: 32KB, 8-way associative. 64 byte line size.

 L2 (MLC): 256KB, 8-way associative. 64 byte line size.

TLB info

 Instruction TLB: 2MB or 4MB pages, fully associative, 7 entries

 Instruction TLB: 4K pages, 4-way associative, 64 entries.

 Data TLB: 4KB or 4MB pages, fully associative, 32 entries.

 Data TLB: 4KB pages, 4-way associative, 64 entries

 Data TLB: 4K pages, 4-way associative, 512 entries.

 Data TLB: 4KB or 4MB pages, fully associative, 32 entries.

 Data TLB: 4KB pages, 4-way associative, 64 entries

 64 byte prefetching.

 Data TLB: 4K pages, 4-way associative, 512 entries.

Found unknown cache descriptors: dd 

Total processor threads: 4

This system has 1 dual-core processor with hyper-threading (2 threads per core) running at an estimated 2.65GHz

You could try this command.

$sudo dmidecode -t cache

Example

$ sudo dmidecode -t cache | grep -iE "leve|installed"

    Configuration: Enabled, Socketed, Level 1

    Installed Size: 32 kB

    Installed SRAM Type: Asynchronous

    Configuration: Enabled, Socketed, Level 2

    Installed Size: 256 kB

    Installed SRAM Type: Burst

    Configuration: Enabled, Socketed, Level 3

    Installed Size: 3072 kB

    Installed SRAM Type: Burst

To see RAM simply add the additional switch -t memory.

$ sudo dmidecode -t cache -t memory

References

• finding L2 cache size in Linux

getconf

getconf -a | grep CACHE

gives:

LEVEL1_ICACHE_SIZE                 32768

LEVEL1_ICACHE_ASSOC                8

LEVEL1_ICACHE_LINESIZE             64

LEVEL1_DCACHE_SIZE                 32768

LEVEL1_DCACHE_ASSOC                8

LEVEL1_DCACHE_LINESIZE             64

LEVEL2_CACHE_SIZE                  262144

LEVEL2_CACHE_ASSOC                 8

LEVEL2_CACHE_LINESIZE              64

LEVEL3_CACHE_SIZE                  20971520

LEVEL3_CACHE_ASSOC                 20

LEVEL3_CACHE_LINESIZE              64

LEVEL4_CACHE_SIZE                  0

LEVEL4_CACHE_ASSOC                 0

LEVEL4_CACHE_LINESIZE              0

Or for a single level:

getconf LEVEL2_CACHE_SIZE

The cool thing about this interface is that it is just a wrapper around the POSIX sysconf C function (cache arguments are non-POSIX extensions), and so it can be used from C code as well.

Tested in Ubuntu 16.04.

x86 CPUID instruction

The CPUID x86 instruction also offers cache information, and can be directly accessed by userland: https://en.wikipedia.org/wiki/CPUID

glibc seems to use that method for x86. I haven't confirmed by step debugging / instruction tracing, but the source for 2.28 sysdeps/x86/cacheinfo.c does that:

__cpuid (2, eax, ebx, ecx, edx);

TODO create a minimal C example, lazy now, asked at: https://stackoverflow.com/questions/14283171/how-to-receive-l1-l2-l3-cache-size-using-cpuid-instruction-in-x86

ARM also has an architecture-defined mechanism to find cache sizes through registers such as the Cache Size ID Register (CCSIDR), see the ARMv8 Programmers' Manual 11.6 "Cache discovery" for an overview.

There are special files exported to /sys sysfs Linux filesystem since 2008:

https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-devices-system-cpu

What:       /sys/devices/system/cpu/cpu*/cache/index*/<set_of_attributes_mentioned_below>

Date:       July 2014(documented, existed before August 2008)

Description:    Parameters for the CPU cache attributes



    allocation_policy:

        - WriteAllocate: allocate a memory location to a cache line

                 on a cache miss because of a write

        - ReadAllocate: allocate a memory location to a cache line

                on a cache miss because of a read

        - ReadWriteAllocate: both writeallocate and readallocate



    coherency_line_size: the minimum amount of data in bytes that gets

                 transferred from memory to cache



    level: the cache hierarchy in the multi-level cache configuration



    number_of_sets: total number of sets in the cache, a set is a

            collection of cache lines with the same cache index



    physical_line_partition: number of physical cache line per cache tag



    shared_cpu_list: the list of logical cpus sharing the cache



    shared_cpu_map: logical cpu mask containing the list of cpus sharing

            the cache



    size: the total cache size in kB



    type:

        - Instruction: cache that only holds instructions

        - Data: cache that only caches data

        - Unified: cache that holds both data and instructions



    ways_of_associativity: degree of freedom in placing a particular block

                of memory in the cache



    write_policy:

        - WriteThrough: data is written to both the cache line

                and to the block in the lower-level memory

        - WriteBack: data is written only to the cache line and

                 the modified cache line is written to main

                 memory only when it is replaced

ID files:

What:       /sys/devices/system/cpu/cpu*/cache/index*/id

Date:       September 2016

Contact:    Linux kernel mailing list <linux-kernel@vger.kernel.org>

Description:    Cache id



    The id provides a unique number for a specific instance of

    a cache of a particular type. E.g. there may be a level

    3 unified cache on each socket in a server and we may

    assign them ids 0, 1, 2, ...



    Note that id value can be non-contiguous. E.g. level 1

    caches typically exist per core, but there may not be a

    power of two cores on a socket, so these caches may be

    numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...

cpuid

Another option is cpuid program. It uses CPUID instructions and does not require root. It also can work throught cpuid Linux kernel module.

cache and TLB information (2):

   0x59: data TLB: 4K pages, 16 entries

   0xba: data TLB: 4K pages, 4-way, 64 entries

   0x4f: instruction TLB: 4K pages, 32 entries

   0xc0: data TLB: 4K & 4M pages, 4-way, 8 entries

   0x80: L2 cache: 512K, 8-way, 64 byte lines

   0x30: L1 cache: 32K, 8-way, 64 byte lines

   0x0e: L1 data cache: 24K, 6-way, 64 byte lines

Note that on common consumer CPUs L1 and L2 caches are per core, while L3 cache is shared by all cores.

if you only want the L3 then grep "cache size" < /proc/cpuinfo should be enough.

However since the way L3 cache is shared among cpu archs differs, its value might need normalization